The present invention relates, in general, to the field of integrated circuit (“IC” or “chip”) devices. More particularly, the present invention relates to a clock generator circuit for supplying a clock signal for distribution throughout the IC, such as a memory IC, and a corresponding method of operation.
There are two existing internal clock generation schemes that are widely known and used in the art.
In a first type of internal clock generation, the internal clock is a buffered version of the external clock. The internal clock high and low times, duty cycle, and frequency are all replications of the external clock signal. There are two main problems with this scheme. First, at very high frequencies the internal clock high time may not be long enough for proper chip operation. In this case not as much clock low time is required and so an internal duty cycle greater than 50% is preferred. Second, at lower frequencies there may be too much clock high time for proper chip operation. At some point enough clock high time has expired to complete all necessary chip functions, with margin, and it would be preferable to start the next function normally associated with the falling edge of the clock.
In a second type of internal clock generation, the internal clock is generated as a fixed-width pulse (“one-shot”), based on the rising edge of the external clock. The width of the internal clock signal is fixed and therefore does not change with frequency. The main problem with this is margin. If the internal clock pulse width is designed to accomplish all necessary chip functions with enough margin, the resultant clock signal is usually too slow for high speed operation. If the internal clock pulse width is designed without sufficient margin, then failures occur no matter how slow the clock frequency is.
The problems cited above as well as other clock signal-based problems are illustrated in the timing diagrams of FIGS. 1-3.
Referring to FIG. 1, the high time of the external clock signal is less than a minimum acceptable time for proper operation of the integrated circuit. The external clock signal is shown as waveform 10A. In a first prior art technique, the internal clock signal is shown as waveform 12A, which is an internally buffered version of the external clock. As discussed above the problem with this technique is that the width of the internal clock signal may be too narrow to complete all necessary chip functions as the external clock signal frequency increases or the duty cycle decreases. In a second prior art technique, the internal clock signal is shown as waveform 14A, in which the width of the clock signal is constant as specified by a one-shot circuit.
Referring to FIG. 2, the high time of the external clock signal is between minimum and maximum acceptable times for proper operation of the integrated circuit. The external clock signal is shown as waveform 10B. In a first prior art technique, the internal clock signal is shown as waveform 12B, which is an internally buffered version of the external clock. In a second prior art technique, the internal clock signal is shown as waveform 14B, in which the width of the clock signal is constant as specified by a one-shot circuit. A problem with this technique is that now the low time of the internal clock signal may not be sufficient for proper chip operation.
Referring to FIG. 3, the high time of the external clock signal is greater than a maximum acceptable time for proper operation of the integrated circuit. The external clock signal is shown as waveform 10C. In a first prior art technique, the internal clock signal is shown as waveform 12A, which is an internally buffered version of the external clock. A problem with this technique is that the falling edge of the internal clock signal with respect to the rising edge of the next external clock signal may be too narrow to complete all necessary chip functions as the external clock signal frequency increases or the duty cycle increases. In a second prior art technique, the internal clock signal is shown as waveform 14C, in which the width of the clock signal is constant as specified by a one-shot circuit.
What is desired is an optimum type of internal clock signal for an integrated circuit such that failures decrease as the part is run at slower frequencies. This correlation results in higher yields as fewer parts are completely thrown away, regardless of how fast or slow they may be.